Timing Closure Techniques for Vivado DS | LAX & Online

Technically Speaking International, INC

Timing Closure Techniques for Vivado DS | LAX & Online

Schedule Your Time
$ 900.00


Please note:  This course is scheduled to run Onsite and Online simultaneously, using the same content and labs.

After completing this comprehensive training, you will have the necessary skills to:

  • Enter primary clock constraints as needed
  • Add generated and virtual clocks were appropriate
  • Determine if constraints are reasonable
  • Apply source-synchronous I/O interface constraints
  • Handle path exceptions, MC, false paths, min/max delays
  • Use case analysis
  • Describe the "baselining" process
  • Properly constrain synchronization circuits
  • Handling clock domain crossing (CDC)
  • Determine when Floorplanning is beneficial
  • Access key reports for design QoR
  • Preserve existing timing

    Course Outline

Day 1

  • HDL Coding Techniques
  • Vivado STA Overview
  • Introduction to Clock Constraints
  • Generated Clocks
  • I/O Constraints and Virtual Clocks
  • Timing Constraints Wizard (Demo)
  • Introduction to Vivado Reports
  • Setup and Hold Timing Analysis
  • Handling Clock-Domain-Crossings (CDC)
  • Detailed Critical Path Analysis
  • Handling Resets
  • Case Analysis
  • Design Preservation (Demo)
  • Floorplanning Overview
  • IP Specific XDC


Topic Descriptions

  • Good HDL coding is the first step to timing closure. Use of resets, conditional statements, inference versus instantiating hard IP.
  • How STA works with Vivado, using fast and slow process corners for analysis, clock pessimism, MMCM impact.
  • Creating primary clock constraints, matching MMCM specification
  • Constraining generated clocks, either user-defined or MMCM/HSSIO
  • System Synchronous input/ouput constraints and virtual clocks
  • Source Synchronous interface requirements and syntax
  • Timing Constraint Wizard for entry and verifying existing constraints
  • Using key Vivado reports for timing analysis and design QoR
  • Properly constraining and analyzing CDCs .
  • Detailed critical path analysis, what to look for to pinpoint cause of timing failure, apply appropriate correction.
  • Recommendations for reset signal, global and local
  • Using case analysis to streamline timing analysis when appropriate
  • Maintaining existing timing results as design is modified
  • Determine circumstances where floorplanning is useful or potentially counter-productive
  • Managing IP specific XDC timing constraints