Session 7. Versal SoC Simulation and Debug (Versal Adopter Series) (Orange County)
Technically Speaking, Inc.
Session 7. Versal SoC Simulation and Debug (Versal Adopter Series) (Orange County)
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$ 900.00
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Description
Session 7. Versal SoC Simulation and Debug
Verification of subsections and system at large
- Best practice Versal development and debug methodology
- Intro to HSDP ( High Speed Debug Port)
- Establishing simulation break-points for PS application and AIE code
- Leveraging Vivado logic analyzer for PL
- Cross-triggering techniques for PL and PS
- Configuration and debugging
- System debugging
- Using trace events for AIE debugging
- ChipScoPy overview
- Hard block debugging
- Using Vitis Analyzer