Workshop Description

This event describes the AMD Versal™ AI Engine architecture, and then walks through the programming requirements in a step-by-step manner. The example is a 32 tap FIR filter with data connections between the AI Engine tiles and the programmable logic (PL).  The workshop also explores coding using both intrinsic(s) and C++ APIs.  Finally, we demonstrate using the FIR library resources, along with basic analyzation and profiling features.

The emphasis of this workshop is on:

• Illustrating the AI Engine architecture
• Designing single AI Engine kernels using the Vitis™ unified software platform
• Reviewing the data movement between AI Engines, between AI Engines via memory and DMA, and between AI Engines to programmable logic (PL)
• Analyzing and debugging kernel performance
• Window, Buffers, and Streaming Data APIs module: Additional information on input and output buffers
• AI Engine APIs: Additional information on vector and accumulator initialization and conversion APIs

After completing this comprehensive training, you will have the necessary skills to:

• Describe the Versal adaptive SoC architecture at a high level
• Describe the various engines in the Versal device and the motivation behind the AI Engine
• Describe the architecture of the AI Engine
• Describe the memory access structure for the AI Engine
• Describe the full application acceleration flow with the Vitis tool
• Enumerate the toolchain for Versal AI Engine programming
• Explain what AI Engine APIs are
• Program a single AI Engine kernel using the Vitis IDE tool

Workshop Outline

Session 1

Versal AI Engine Architecture

• Versal AI Engine Architecture

Introduces the architecture of the AI Engine and its components.

• AI Engine Interfaces

Describes the AI Engine interfaces that are available, including the memory, lock, core debug, cascaded stream, and AXI-Stream interfaces.

• Versal AI Engine Memory and Data Movement

Describes the memory module architecture for the AI Engine and how memory can be accessed by the AI Engines in the AI Engine arrays.

Vitis Tool Flow

• Versal AI Engine Tool Flow

Reviews the Vitis tool flow for the AI Engine and demonstrates the full application acceleration flow for the Vitis platform.

The Programming Model

• Scalar and Vector Data Types

Provides an AI Engine functional overview and identifies the supported vector data types and high-width registers for allowing single-instruction multiple-data (SIMD) instructions.

• AI Engine APIs

Describes what AI Engine APIs are, the three types of vector manipulation operations using AI Engine APIs (load and store, element conversion, and lane insertion/extraction), multiplication functions, and application-specific functions.

Session 2

Design Analysis

• Vitis Analyzer

Describes the different reports generated by the tool and how to view the reports that help to optimize and debug AI Engine kernels using the Vitis analyzer tool.

The Programming Model

• Windows, Buffers, and Streaming Data APIs

Describes window, i/o buffers and streaming data APIs and reviews the various buffer operations for kernels.

• The Programming Model: Single Kernel

Reviews the AI Engine kernel programming flow for programming and building a single kernel. Also illustrates the steps to create, compile, simulate, and debug a single kernel program using the Vitis IDE tool.

• The Programming Model: Introduction to the Adaptive Data Flow (ADF) Graph

Provides the basics of the data flow graph model and graph input specifications for AI Engine programming. Also reviews graph input specifications, such as the number of platforms and ports.