Designing with VHDL | Online

Technically Speaking International, INC

Designing with VHDL | Online

Schedule Your Time
$ 2400.00



Note: This class is run in conjunction with East Coast based BLT.  Hence class start time for the West Coast is 6 am. PST.

Course Description

This comprehensive course is a thorough introduction to the VHDL language. The emphasis is on writing solid synthesizable code and enough simulation code to write a viable testbench. Structural, register transfer level (RTL), and behavioral coding styles are covered. This class addresses targeting Xilinx devices specifically and FPGA devices in general. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn best coding practices that will increase your overall VHDL proficiency and prepare you for the Advanced VHDL course.

In this three-day course, you will gain valuable hands-on experience. Incoming students with little or no VHDL knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations.

Course Outline

Day 1

  • HDL Design Flow Overview
  • Hardware Modeling Concepts
  • VHDL Design Units
  • Lab 1: Creating Hierarchy
  • Introduction to Testbenches
  • Lab 2: Build Testbench, Run Simulation ▪ VHDL Signals & Datatypes
  • Operators and Expressions
  • Lab 3: Build RAM / ROM Module
Day 2


  • Concurrent & Sequential Statements
  • Lab 4: Build Clock Divider – Address Counter
  • Controlled Operation Statements, If/else – Case -Loops ▪ Lab 5: Build Binary Counter with Generics
  • Using VITAL
  • Lab 6: Running Timing Simulation
  • Behavioral to RTL Coding

Day 3

  • Coding FSMs in VHDL

  • Lab 7: Modify & Test Existing FSM Source Code

  • Targeting Xilinx FPGAs

  • Lab 8: Xilinx Tool Flow, Download to Demo Board

  • VHDL Subprograms, Functions and Procedures

  • Advanced Process Statements

  • Lab 9: Simulation with VHDL Text I/O

Lab Descriptions

The labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. You will write, synthesize, simulate, and implement all the labs. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits.

* This course does not focus on any particular architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.
After completing this comprehensive training, you will have the necessary skills to:

  • Implement the VHDL portion of coding for synthesis

  • Identify the differences between behavioral and structural coding


  • Distinguish coding for synthesis versus coding for simulation

  • Use scalar and composite data types to represent information

  • Use concurrent and sequential control structure to regulate information flow

  • Implement common VHDL constructs (Finite State Machines [FSMs], RAM/ROM data structures)

  • Simulate a basic VHDL design

  • Write a VHDL testbench and identify simulation-only constructs

  • Identify and implement coding best practices

  • Optimize VHDL code to target specific silicon resources within the Xilinx FPGA

  • Create and manage designs within the Vivado Design Suite environment