COURSE OUTLINE
Day 1
>
Introduction
> Transmission Lines
> Lab 1: Mentor or Cadence
> IBIS Models
> Lab 2: Mentor or Cadence
> Lab 3: Mentor or Cadence
> High-Speed Clock Design
> Lab 4: Mentor or Cadence
> SRAM Requirements
> Lab 5: Mentor or CadenceDay 2
>
Physical PCB Structure
> On-Chip Termination
> SDRAM Design
> Lab 6: Mentor
> Managing an Entire Design
LAB DESCRIPTION
Mentor Lab 1:
Opening the appropriate
Mentor simulator
Mentor Lab 2:
Hands-on signal integrity observation
of reflection and propagation effects
Mentor Lab 3:
Using an IBIS simulator to study basic transmission
line effects
Mentor Lab 4:
Using saved simulation information
to perform power calculation. Also, additional
clock simulations
Mentor Lab 5:
Observing the effects of coupling on transmission
lines
Mentor Lab 6:
Demonstrating how an SDRAM module can be handled
with an EBD model
Cadence Lab 1:
Opening the appropriate
Cadence simulator
Cadence Lab 2:
Analysis of a simple clock net
Cadence Lab 3:
Signal integrity effects caused by multidrop clock
networks
Cadence Lab 4:
Crosstalk analysis
Cadence Lab 5:
Address and data analysis
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