Introduction to Verilog
 This
comprehensive course is a thorough introduction to
the Verilog language. The emphasis is on
writing Register Transfer Level (RTL) and behavioral
source code. This class addresses targeting
Xilinx devices specifically and FPGA devices in
general. The information gained can be applied
to any digital design by using a top-down synthesis
design approach. Insightful lectures are
combined with practical lab exercises to reinforce
key concepts. You will also learn advanced
coding techniques that will increase your overall
Verilog proficiency and enhance your FPGA
optimization. The course will cover Verilog
1995 and 2001.Incoming students with
little or no Verilog knowledge will finish this
course empowered with the ability to write efficient
hardware designs and perform high-level HDL
simulations....DOWNLOAD
INTRODUCTION TO VERILOG COURSE DETAIL
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At-A-Glance |
Schedule |
- Course
No: LANG12000-8-ILT
- Course Duration: 3 Days
- Price: USD $1,500
or 15 Xilinx
Training Credits
- Practical HDL Multimedia CD:
USD $300 or 3 Xilinx Training Credits
- Level:
Advanced
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Prerequisites
> Basic digital design knowledge
- Software
Tools
> Xilinx ISE™ 8.1i
> Xilinx ISIM Simulator
> Synplicity Synplify Pro
> Synopsys SmartModels
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COURSE OUTLINE
Day 1
> Hardware Modeling Overview
> Verilog Language Concepts
> Memories, Modules, and Ports
> Lab 1: Building Hierarchy
> Introduction to Testbenches
> Lab 2: Verilog Simulation and RTL Verification
> Operators and ExpressionsDay 2
> Data Flow-Level Modeling
> Lab 3: Memory
> Verilog Procedural Statements
> Controlled Operation Statements
> Lab 4: n-bit Binary Counter and RTL Verification
> Advanced Language Concepts
> Lab 5: Comparator
Day 3
> Tasks and Functions
> Lab 6: Arithmetic Logic Unit
> Finite State Machines
> Targeting Xilinx FPGAs
> Lab 8: Calculator
LAB DESCRIPTION
The labs for this course provide a practical
foundation for creating RTL code. Labs are
written, synthesized, behaviorally simulated, and
implemented by the student. The focus of the
labs is to write code that will optimally infer
reliable and high-performance circuits.
All aspects of the design flow are covered in the
labs. The labs culminate in a functional
calculator that students verify in simulation.
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