Intro to VHDL
 This
course will give you a thorough introduction to the
VHDL language. The emphasis is on writing
Register Transfer Level (RTL) and behavioral source
code. The class addresses targeting Xilinx
devices specifically and FPGA devices in general.
The information gained can be applied to any digital
design by using a top-down synthesis design
approach. Insightful lectures are
combined with practical lab exercises to reinforce
key concepts.
You will also learn advanced coding techniques
that will increase your overall VHDL proficiency and
prepare you for the Advanced VHDL course.
Incoming students with little or no VHDL knowledge
will finish this course empowered with the ability
to write efficient hardware designs and perform
high-level HDL simulations....DOWNLOAD
INTRO TO VHDL COURSE DETAIL
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At-A-Glance |
Schedule |
- Course
No: LANG1100-8-ILT
- Course Duration: 3 Days
- Price: USD $1,500
or 15 Xilinx
Training Credits
- PracticalHDL Multimedia CD:
USD $300 or 3 Xilinx Training Credits
- Level:
Advanced
-
Prerequisites
> Basic digital design knowledge
- Software
Tools
> Xilinx ISE™ 8.1i
> Xilinx ISIM Simulator
> Synplicity SynplifyPro
> Synopsis SmartModels
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COURSE OUTLINE
Day 1
> Course Agenda
> Hardware Modeling Overview
> Language Concepts
> Lab 1: Building Hierarchy
> Introduction to Testbenches
> Lab 2: VHDL Simulation and RTL Verification
> Signals and Data Types
> VHDL Operators and Expressions
> Lab 3: Memory and RecordDay 2
> Concurrent and Sequential Statements
> Advanced Process Statements
> Lab 4: n-bit Binary Counter and RTL
Verification
> Controlled Operation Statements
> Lab 5: Comparator
> Behavioral to RTL Coding
Day 3
> Finite State Machines
> Lab 6: Arithmetic Logic Unit
> VITAL: VHDL Initiative toward ASIC Libraries
> Lab 7: State <achines
> Targeting Xilinx FPGAs
> Functions and Procedures
> Lab 8: Calculator
LAB DESCRIPTION
The labs for this course provide a practical
foundation for creating RTL code. Labs are
written, synthesized, behaviorally simulated, and
implemented by the student. The focus of the
labs is to write code that will optimally infer
reliable and high-performance circuits.
All aspects of the design flow are covered in the
labs. The labs culminate in a functional
calculator that students verify in simulation.
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