COURSE OUTLINE
Day 1
> Introduction
to AccelDSP Design Flow
> Synthesizable MATLAB
> Quantization
> Multirate Design
> Using AccelWare IP
> Overview of FPGA ArchitectureDay 2
>
Design Exploration
> Adding Hardware Control
> Coding for Hardware Performance
> Synthesizing Complex Numbers
> Interfacing to System Hardware
> Exporting to System Generator
LAB DESCRIPTION
Lab 1: Getting Started.
Learn the basic design flow through the AccelDSP
Synthesis Tool.
Lab 2: Synthesizable MATLAB.
Modify an unsynthesizable MATLAB design into a
design that can be synthesized by AccelDSP.
Lab 3: Quantization.
Specify, monitor, and control bit growth in the
synthesized design.
Lab 4:
Multirate Design.
Set up behavioral MATLAB to model the effects of
decimation by 2. Create a synthesizable polyphase
decimation filter in MATLAB and implement the filter
in a Xilinx FPGA.
Lab 5: Using AccelWare.
Replace a MATLAB-based polyphase decimation filter
with an equivalent Firdecim AccelWare IP block.
Lab 6:
Design Exploration.
Apply the design exploration features of AccelDSP to
optimize a design for area and performance.
Lab 7: Adding Hardware Control. Modify
the source MATLAB of a FIR filter to add a serial
coefficients load feature.
Lab 8:
Coding for Hardware Performance. Learn
MATLAB coding techniques to take advantage of
even-symmetric coefficients and drive performance
over 300 MHz.
Lab 9: Synthesizing Complex Numbers.
Explore the methods available for synthesizing
designs that use complex numbers.
Lab 10: Interfacing to Hardware.
Connect the AccelDSP-generated interface signals to
a larger HDL design.
Lab 11: Export to System Generator.
Export a MATLAB-based design into a System Generator
block and merge the block into a larger System
Generator design.
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