Xilinx Fundamentals of FPGA Design Course by TSI

Fundamentals of FPGA Design
Use the ISE™ software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.

This course covers the ISE 8.2i features, such as the architecture Wizard and the Pin and Area Constraint Editor (PACE). Other topics include design planning, implementation options, and global timing constraints. For more emphaasis on improving the overall design performance, take the follow-up course Designing for Performance, which builds on the basic principles covered in this course...DOWNLOAD XILINX FUNDAMENTALS OF FPGA DESIGN COURSE DETAIL

At-A-Glance

Schedule

Course No: FPGA13000-8.2-ILT
Course Duration: 1 Day
Price: USD $500
or 5 Xilinx Training Credits
Level: Fundamental
Prerequisites
> Basic FPGA Architecture:
   Slice and I/O Resources REL*
> Basic FPGA Architecture:
   Memory and Clocking REL*
> Working HDL knowledge
   (VHDL or Verilog)
> Digital design experience
Software Tools
> Xilinx ISE™ 8.2i

*Recorded e-Learning

COURSE OUTLINE

Day 1
> Course Agenda
> Review of Basic FPGA Architecture
> Xilinx Tool Flow
> Lab 1: Xilinx Tool Flow Lab
> Reading Reports
> Architecture Wizard and PACE
> Lab 2: Architecture Wizard and PACE Lab
> Global Timing Constraints
> Lab 3: Global Timing Constraints Lab
> Implementation Options
> Lab 4: Implementations Options Lab
> Synchronous Design Techniques
> Course summary

LAB DESCRIPTION

Lab 1: Xilinx Tool Flow. Create a new project in the ISE project Navigator and use the Architecture Wizard and PACE tool in the design process. Implement a design by using default software options. The design will be simulated.

Lab 2: Architecture Wizard and PACE. Use the Architecture Wizard to customize a DCM and incorporate the DCM into the design. Use PACE to assign pin locations and implement the design.

Lab 3: Global Timing Constraints. Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint.

Lab 4: Implementation Options. Adjust process properties and I/O configuration options to improve the design performance.