Xilinx Designing with the Virtex-4 Family Course by TSI

Designing with the Virtex-4 Family
Interested in learning how to utilize Virtex™-4 FPGA architectural resources effectively? This course focuses on understanding and utilizing several of the new and enhanced resources found in our newest device. Topics covered include an overview of the Virtex-4 FPGA; the Digital Clock Manager (DCM) and Phase-Matched Clock Divider (PMCD); global and regional clocking techniques; memory and FIFO; and source-synchronous resources. A combination of modules and labs allow for practical hands-on application of the principles taught in this course.

Prerequisite courses required include Fundamentals of FPGA Design and Designing for Performance...DOWNLOAD XILINX DESIGNING WITH THE VIRTEX-4 FAMILY COURSE DETAIL

At-A-Glance

Schedule

Course No: V4-23000-8-ILT
Course Duration: 2 Days
Price: USD $1,000
or 10 Xilinx Training Credits
Level: Intermediate
Prerequisites
> Fundamentals of FPGA
   Design course
> Designing for Performance course
> Understanding of the Virtex-II Pro,
    Virtex-II Pro X FPGA architecture
Software Tools
> Xilinx ISE™ 8.1i
> Xilinx XST

COURSE OUTLINE

Day 1
> Introduction
> Product Overview
> DCM Clock Management
> PMCD Clock Management
> Lab 1: DCM Clocking
> Clock Networks
> Lab 2: Clocking Resources

Day 2
> Day Two Overview
> I/O and Source-Synchronous Resources
> Lab 3: Utilizing Source-Synchronous I/O Resources
> Block RAM Memory Resources
> FIFO16 Memory Resources
> Lab 4: Utilizing Block RAM and FIFO16
> XtremeDSP™ Technology Slice
> Lab 5: Utilizing XtremeDSP Technology Resources
> Configuration
> Day Two Review

LAB DESCRIPTION

Lab 1: DCM Clocking. Designing a clock management scheme with DCMs and PMCDs.

Lab 2: Clocking Resources. Utilizing global and regional clock networks.

Lab 3: Utilizing Source-Synchronous I/O Resources. Creating a source-synchronous design interface for a network application.

Lab 4: Utilizing Block RAM and FIFO16. Utilizing new block RAM features and FIFO16-dedicated resources.

Lab 5: Utilizing XtremeDSP Technology Resources. Utilizing the DSP48 block.