Xilinx® ATP Courses > Designing with the Virtex™-5 LX Platform FPGA
Designing with the Virtex-5 LX Platform FPGA
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Interested in learning how to effectively utilize Virtex™-5 FPGA architectural resources? Targeted towards experienced Xilinx users who have already completed Fundamentals of FPGA Design and Designing for Performance and have a comprehensive knowledge of Virtex-4 FPGAs, this course focuses on understanding as well as designing into several of the new and enhanced resources found in our newest device.  

Topics covered include a Virtex-5 FPGA overview, new CLB, DCM and PLL, global and regional clocking techniques, memory, DSP and arithmetic logic, and source-synchronous resources.  A combination of modules and labs allow for practical hands-on application of the principles taught.

Note: Recorded e-Learning modules will also be available. For all other regions, only the recorded e-Learning modules will be available. Also note that the initial course material covers the Virtex-5 LX FPGA ...DOWNLOAD XILINX DESIGNING WITH THE VIRTEX-5 LX PLATFORM COURSE DETAIL

At-A-Glance Schedule
  • Course No:  V5LX-21000-8-ILT
  • Course Duration:   2/3rd Day
  • Price:  USD $300
    or  3 Xilinx Training Credits
  • Level: Intermediate
  • Prerequisites
    > Fundamentals of FPGA Design
      
     course
    > Designing for Performance course
    > Designing with the Virtex-4 Family
        course or comprehensive
        knowledge of the Virtex-4 FPGA
  • Software Tools
    > Xilinx ISE
    8.2i
    > Synplicity Synplify Pro 8.6
    > Mentor Graphics Precision 2005c

 

 

 

COURSE OUTLINE

Day 1

> Virtex-5 FPGA Overview
> CLB Resources
> Clocking Resources
> Lab 1: Clocking Resources Lab
> I/O Resources
> Memory Resources
> XtremeDSP Technology Resources
> Lab 2: DSP48E Resources Lab

LAB DESCRIPTION

The labs will provide practical hands-on application
of the principles taught throughout the course.

Lab 1: Clocking Resources.  In this lab, you will create a PLL core by using the Architecture Wizard to generate a PLL core to instantiate in your design. You will then simulate the PLL core to verify functionality.

Lab 2: DSP48E Resources.  In this lab, you will create a Multiplexer by using the XtremeDSP™ technology (DSP48E) resource through primitive instantiation. You will then simulate the resources to verify functionality.

 

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