Xilinx Designing a LogiCORE Express System Course by TSI

Designing a LogiCORE PCI Express System
By learning PCI Express core protocol fundamentals, designers will gain a working knowledge of how PCI Express can be used in their systems. This course focuses on the PCI Express protocol subjects that designers, using the Xilinx PCI Express core, should understand to complete their designs faster and more easily. Students will also be introduced to each Xilinx PCI Express core product and will gain intimate knowledge of how the PCI Express core operates...DOWNLOAD XILINX DESIGNING A LOGICORE PCI EXPRESS SYSTEM COURSE DETAIL

At-A-Glance

Schedule

Course No: PCIE28000-8-ILT
Course Duration: 2 Days
Price: USD $1,000
or 10 Xilinx Training Credits
Level: Intermediate
Prerequisites
> Basic PCI and/or PCI-X
    protocol knowledge
> Basic knowledge of Verilog or VHDL
> Basic experience with commonly
   used simulation tools like ModelSim
> Basic knowledge of
   Xilinx ISE™ software
Software Tools
> Xilinx ISE™ 8.1i
> Mentor Graphics ModelSim 6.0c PE

COURSE OUTLINE

Day 1
> Overview
> Layers and Channels
> TLP Fields and Packet Routing
> PCI Express Local Link Interface
> Lab 1: Using the Local Link Interface
> PCI Express Configuration Space
> Lab 2: Exploring the Configuration Space

Day 2
> TLP Request and Completion Packets
> Generating Interrupts
> PCI Express Core Design Considerations
> Lab 3: Designing with the PCI Express Core
> PCI Express DMA Design Example
> Lab 4: PCI Express DMA Design Example
> Clocking and Other Physical Layer Topics
> Xilinx PCI Express Solutions
> Lab 5: Generating a Xilinx PCI Express Core

LAB DESCRIPTION

Lab 1: Using the Local Link Interface. Introduces the PCI Express core design that will also be used in
Lab 2. It familiarizes you with the core user application interface (Local Link) and with modifying the design to change the packets being sent.

Lab 2: Exploring the Configuration Space. Reinforces lessons learned in the previous modules by having you decode configuration packets to understand the requirements in configuring the core. In addition, you will see how to implement user configuration space.

Lab 3: Designing with the PCI Express Core. Takes an in-depth look at designing with the core. You will become familiar with packet ordering and credits available.

Lab 4: PCI Express DMA Design Example. Allows you to see how a simple, single-channel DMA example can be used with the PCI Express Core. You will also become familiar with allocating completion space for inbound completions.

Lab 5: Generating a Xilinx PCI Express Core. Illustrates using the CORE Generator™ software to generate a core. The core is then implemented and you can verify the implementation by studying the various reports created by the Xilinx tools.