COURSE OUTLINE
Day 1 > Review of Fundamentals of FPGA
Design
> Designing with Virtex™-4 FPGA Resources
> CORE Generator Software System
> Lab 1: CORE Generator Software System
> Designing Clock Resources
> FPGA Design Techniques
> Synthesis Techniques
> Lab 3; Synthesis TechniquesDay 2
> Achieving Timing Closure
> Lab 4: Review of Global Timing
Constraints
> Timing Groups and OFFSET cONSTRAINTS
> Path-Specific Timing Constraints
> Lab 5: Achieving Timing Closure
> Advanced Implementation Options
> Lab 6: Designing for Performance
> Power Estimation (Optional)
> ChipScope™ Pro Analyzer (Optional)
> Lab 8: ChipScope Pro Analyzer (Optional)
> Course Summary
LAB DESCRIPTION
Lab 1: CORE Generator Software System.
Create a core, instantiate the core into VHDL or
Verilog source code, and run behavioral simulation.
Lab 2: Designing Clock Resources.
Use the Clocking Wizard to configure DCMs and global
clock buffer resources.
Lab 3: Synthesis Techniques.
Experiment with different synthesis options and view
the results. Versions of this lab are
available for Synplicity
Synplify Pro, Precision RTL, and Xilinx XST
software.
Lab 4: Review of Global Timing
Constraints. Use the Constraints Editor to
enter global timing constraints.
Lab 5: Achieving Timing Closure.
Review timing reports and enter path-specific timing
constraints to meet performance goals.
Lab 6: Designing for Performance.
Improve performance and maximize results solely with
implementation options.
Lab 7: FPGA Editor Demo. Use
the FPGA Editor to view a design and add a probel to
an internal net.
Lab 8: ChipScope Pro Analyzer.
Add an internal logic analyzer to a design to
perform real-time debugging.
|