Xilinx Designing for Performance Course by TSI

Designing for Performance, FPGA3
Attending this course will help you create more efficient designs. You learn how to fit your design into a smaller FPGA or a lower speed grade for reducing system costs. By mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.

Recommended prerequisite course is Fundamentals of FPGA Design or equivalent knowledge of FPGA architecture features...DOWNLOAD XILINX DESIGN FOR PERFORMANCE COURSE DETAIL

At-A-Glance

Schedule

Course No: FPGA23000-11-ILT (v1.0)
Course Duration: 2 Days
Price: USD $1,000
or 10 Xilinx Training Credits
Level: Intermediate
Prerequisites
> Essentials of FPGA Design
    course or equivalent knowledge
     of FPGA architecture features;
     the Xilinx implementation software
     flow and implementation options;
     reading timing reports; basic FPGA
     design techniques; global timing
     constraints and the use
    of the Xilinx Constraints Editor
Intermediate HDL knowledge (VHDL or Verilog)
Solid digital design background
Software Tools
> ISE Design Suite:
System Edition 11.1
> Synplicity Synplify Pro
software C-2009.03

COURSE OUTLINE

Day 1
> Review of Fundamentals of FPGA Design
> Designing with Virtex™-5 FPGA Resources
> CORE Generator Software System
> Lab 1: CORE Generator Software System
> Lab 2:Designing Clock Resources
> FPGA Design Techniques
> Synthesis Techniques
> Lab 3: Synthesis Techniques

Day 2
> Achieving Timing Closure
> Lab 4: Review of Global Timing Constraints
> Timing Groups and OFFSET Constraints
> Path-Specific Timing Constraints
> Lab 5: Achieving Timing Closure
> Advanced Implementation Options
> Lab 6: Designing for Performance
> Lab 7: FPGA Editor Demo (optional)
> ChipScope™ Pro Analyzer (Optional)
> Lab 8: ChipScope Pro Analyzer (Optional)

LAB DESCRIPTION

Lab 1: CORE Generator Software System. Create a core, instantiate the core into VHDL or Verilog source code, and implement the design.

Lab 2: Designing Clock Resources. Use the Clocking Wizard to configure DCMs and global clock buffer resources. Instantiate these resources and implement
the design.

Lab 3: Synthesis Techniques. Experiment with different synthesis options and view the results. Versions of this lab are available for the Xilinx XST and Synplify Pro, software.

Lab 4: Review of Global Timing Constraints. Use the Constraints Editor to enter global timing constraints.

Lab 5: Achieving Timing Closure. Review timing reports and enter path-specific timing constraints to meet performance goals.

Lab 6: Designing for Performance. Improve performance and maximize results solely with implementation options.

Lab 7: FPGA Editor Demo. Use the FPGA Editor to view a design and add a probe to an internal net.

Lab 8: ChipScope Pro Software (optional). Add an internal logic analyzer to a design to perform real-time debugging.