DSP Implementation
Techniques for FPGAs
 This
course shows you how to take advantage of the
features available in the Xilinx FPGA architecture,
including the Virtex™-4FPGA,
and describes how DSP algorithms can be implemented
efficiently. The techniques also demonstrate which
decisions at the system level have the greatest
impact on the implementation process and product
costs....DOWNLOAD
DSP IMPLEMENTATION TECHNIQUES FOR FPGAs COURSE DETAIL
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At-A-Glance |
Schedule |
- Course
No: DSP20000-7-ILT
- Course Duration: 3 Days
- Price: USD $1,800
or 18 Xilinx
Training Credits
- Level:
Advanced
-
Prerequisites
Basic understanding of digital signal
process theory, including: Sample
Rates, Finite Impulse Response (FIR) and
Infinite Impulse Response (IIR) filters,
Oscillators and mixers, and Fast Fourier
Transform
(FFT) algorithm
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COURSE OUTLINE
Day 1
> DSP terminology and acronyms
> Sample rates and bit widths used in DSP
applications
> DSP building blocks and processing requirements
> Numbering formats, range, and precision
> Mathematical operations using a variety of formats
> Structure and resources of Xilinx devices
> Estimating DSP building block sizesDay 2
> Implementing the multiplication function
> Bid-width impact on system-level decisions
> Block versus distributed memory
> SRL16E and the delay function
> Memory aspect rations and their manipulation
> FIR filter specifications and implementation
> Selecting a technique for a given specification
> Effects of half-band and interpolated filters
Day 3
> Options to be considered with multiple channels
> Interpolation and decimation
> Rate changing and its effect on FIR filter choice
> Filtering algorithms that exploit device
architecture
> Importance of connectivity versus isolated
functions
> Datapath--numeric controlled oscillators and
mixers
> Strategies for FFT implementation
> Achieving bandwidth requirements of the FFT
> Using the FPGA as an efficient co-processor
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