Xilinx Course Training: DSP Design Using System Generator

DSP Design Using System Generator
This course allows you to explore the System Generator tool and to gain the expertise you need to develop advanced, low-cost DSP designs. This intermediate course in implementing DSP functions focuses on learning how to use System Generator for DSP, design implementation tools, and hardware-in-the-loop verification. Through hands-on exercises, you will implement a design from algorithm concept to hardware verification by using Xilinx FPGA capabilities...DOWNLOAD DSP DESIGN USING SYSTEM GENERATOR COURSE DETAIL

At-A-Glance

Schedule

Course No: dsp11000-82-ILT (v1.0)
Course Duration: 2 Days
Price: USD $1,200
or 12 Xilinx Training Credits
Level: Intermediate
Prerequisites
> Experience with MATLAB
and Simulink
Basic understanding of
sampling theory
Software Tools
> Xilinx ISE™ 8.2i SP1 with
IP update 1
> Xilinx System Generator 8.2
> The MathWorks MATLAB
with Simulkink R14 SP3

COURSE OUTLINE

Day 1
> Introduction to System Generator
> Simulink Basics
> Lab 1: Using Simulink
> Basic Xilinx Design Capture
> Lab 2: Getting Started with Xilinx System Generator
> Lab 3: Signal Routing
> Implementing System Control
> Lab 4: Implementing System Control

Day 2
> Multi-Rate Systems
> Lab 5: Designing a MAC-based FIR Using
the DSP48 Slice
> Filter Design
> Lab 6: Designing a FIR Filter
Using the FIR Compiler Block
> Memories
> Lab 7: Designing with Shared Memories
> Achieving Higher Performance
> Lab 8: Improving Design Performance

LAB DESCRIPTION

Lab 1: Using Simulink - Learn how to use Simulink toolbox blocks and design a system. Understand the effect sampling rate.

Lab 2: Getting Started with Xilinx Generator - Design a DSP48-based 12 x 8 MAC. Perform hardware-in-the-loop verification.

Lab 3: Signal Routing - Design padding and upadding logic using signal routing blocks.

Lab 4: Implementing System Control - Design an address generator circuit by using blocks and Mcode.

Lab 5: Designing a MAC-Based FIR Using the DSP48 Slice - Using a bottom-up approach, design a MAC-based bandpass FIR filter and verify through hardware-in-the-loop.

Lab 6: Designing a FIR Filter Using the FIR Compiler Block - Design a bandpass FIR filter by using the FIR Compiler block to demonstrate increased productivity.

Lab 7: Designing with Shared Memories - Learn to use multiple System Generator blocks to design and implement a multi-clock domain system.

Lab 8: Improving Design Performance - Use the Timing Analyzer block and other techniques to improve system performance.