Xilinx Advanced FPGA Implementation Course by TSI

Advanced FPGA Implementation
This course tackles the most sophisticated aspects of the ISE™8.1i tool suite and Xilinx hardware. Eight labs provide hands-on experience in this two-day course and cover Synplicity's Synplify, Mentor's Precision, and the Xilinx XST tools.

This course requires the Fundamentals of FPGA Design and Designing for Performance courses as prerequisites. An intermediate knowledge of Verilog or VHDL is strongly recommended as is at least six months' design experience with Xilinx tools and FPGAs. The lecture material in this course covers the ISE software 8.1i tools and the Virtex™-II and Virtex-4 FPGAs....DOWNLOAD ADVANCED FPGA IMPLEMENTATION COURSE DETAIL

At-A-Glance

Schedule

Course No:
FPGA33000-8-ILT
Course Duration: 2 Days
Price: USD $1,000
or 10 Xilinx Training Credits
Level: Advanced
Prerequisites
> Fundamentals of FPGA Design
> Designing for Performance
> Intermediate knowledge of Verilog
    or VHDL is strongly recommended
> At least six months' design
    experience with Xilinx tools
    and FPGAs
Software Tools
> Xilinx ISE™8.1i
> Synplicity Synplify
> Mentor Precision
> Xilinx XST

COURSE OUTLINE

Day 1
> Introduction
> Lab 1: Timing Analyzer, Constraints,
and Closure Review
> Section 1: Advanced Implementation Control
> UCF Editing
> Lab 2: UCF
> Command Line Implementation
> Lab 3: Scripting
> Creating Your Own RPM
> Lab 4: RPM
> Section 2: Timing Enhancement, Fortification,
and Preservation
> Divide and Conquer Design Techniques
> Floorplanner: Effective Layout

Day 2
> Lab 5: Divide and Conquer Design Techniques
> Section 3: Reduce Debug Time
> FPGA Editor: Viewing and Editing a Routed Design
> Lab 6: FPGA Editor
> Lab 7: Reduce Clock Period

LAB DESCRIPTION

The labs will be based on Xilinx ISE 8.1i software.

Lab 1: Timing Analyzer, Constraints,
and Closure. Create global timing constraints, read timing reports, apply path-specific constraints (multi-cycle and false paths), and apply advanced implementation options.

Lab 2: UCF. Write constraints directly into a UCF file to guide the performance results of implementation.

Lab 3: Scripting. Write program commands into a batch file to implement design. Then modify program switches to obtain the greatest possible performance from the design.

Lab 4: RPM. Create an RPM in a UCF file. Use the Timing Analyzer to find a path that is not meeting timing constraints and identify the components of that path. RLOC the components to create the RPM and improve timing for that path.

Lab 5: Divide and Conquer Design Techniques. Use incremental design techniques and Floorplanner for effective implementation of "divide and conquer" techniques.

Lab 6: FPGA Editor. Use the FPGA Editor to view and edit a design. Analyze the contents of a CLB; add a probe; remove, place, and modify components; and analyze long nets.

Lab 7: Reduce Clock Period. Use all of your obtained knowledge to reduce the clock period delay.