Advanced FPGA
Implementation, FPGA4
 This
course tackles the most sophisticated aspects of the
ISE™11.1
tool suite and Xilinx hardware. Seven labs
provide hands-on experience in this two-day course
and cover the Xilinx Synthesis Technology (XST)
tools.
This course requires the
Fundamentals of FPGA Design and
Designing for Performance courses as
prerequisites. An intermediate knowledge of
Verilog or VHDL is strongly recommended as is at
least six months' design experience with Xilinx
tools and FPGAs. The lecture material in this
course covers the ISE software 11.1 tools and the Virtex®-5
and Spartan®
-3EFPGAs....DOWNLOAD
ADVANCED FPGA IMPLEMENTATION COURSE DETAIL
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At-A-Glance |
Schedule |
- Course
No:
- FPGA33000-11-ILT (v1.0)
- Course Duration: 2 Days
- Price: USD $1,000
or 10 Xilinx
Training Credits
- Level:
Advanced
-
Prerequisites
> Essentials of FPGA Design
> Designing for Performance
> Intermediate knowledge of Verilog
or
VHDL is strongly recommended
> At least six months' design
experience
with Xilinx tools
and FPGAs
- Software
Tools
> Xilinx ISE Design Suite:
System Edition 11.1
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ADVANCE FPGA IMPLEMENTATION
LAB DESCRIPTIONS
> Lab 1: Timing Closure Review -- Use the
Constraints Editor to enter timing constraints.> Lab 2: UCF
Editing -- Write constraints directly into a UCF
file to guide the performance results.
> Lab 3: Advanced I/OP Timing -- Compose timing
constraints for an I/O interface. Analyze the
timing and determine changes to optimize the
interface timing.
> Lab 4: Tcl Scripting -- Write ISE tool control
commands in Tcl script files to create a project and
implement the design. Explore how the Tcl
interface is integrated with the Project Navigator
tool.
> Lab 5: SmartGuide Technology -- Utilize
SmartGuide technology to preserve the timing results
from one iteration to the next.
> Lab 6: Floorplanning -- Implement a design by
using floorplanned constraints to enhance the timing
results over a design without floorplanning.
> Lab 7: Advance FPGA Editor -- Use the FPGA
to view and edit a design. Rapidly locate and
swap signals of interest for ChipScope tool cores.
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