Advanced ModelSim
for Verilog
 This
comprehensive one day course offers a balance of
language and tool specific topics that can greatly
improve design verification results and enhance
engineering productivity.
The fast-paced course covers how to fully leverage
Verilog File I/O for both reading input stimulus
from, and writing simulation results to external
files. It also covers ModelSim specific
features such as basic scripting, automated waveform
comparison and Code coverage.
This class affords existing Verilog designers the
opportunity to quickly apply advanced simulation
techniques that immediately save time, promote
consistency and yield an overall more robust design
and verification strategy...DOWNLOAD
TSI ADVANCED MODELSIM FOR VERILOG
COURSE DETAIL
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At-A-Glance |
Schedule |
- Course
No: TSI-AMSEVER-8-ILT
- Course Duration: 1 Day
- Price: USD $600
- PracticalHDL Multimedia CD:
USD $145
- Level:
Intermediate to Advanced
- Prerequisites
> Basic
- Software
Tools
> ISE™
8.2i
> ModelSim 6.2 Simulator
> Xilinx XST™
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COURSE OUTLINE
Day 1
>
Advanced ModelSim Features
> Verilog tasks and functions and procedures
>
Intro to Verilog File I/O
>
Lab 1: Read input stimulus from external file
> Advanced Verilog File I/O Concepts
> Lab 2: Compare simulation results, write to file
> Using ModelSim Code Coverage Features
> Lab 3: Measure code coverage, improve scores
LAB DESCRIPTION
The labs for this course offer a practical hands-on
opportunity to create robust and re-usable
verification strategies. Each exercise is carefully
constructed to permit discovery while exploring
options and tradeoffs.
In addition to the comprehensive step-by-step
instructions, the lab documentation also provides
additional insight regarding the tools, procedures
or best-case practices.
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