Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE® 12.1 design suite and Xilinx hardware. Seven labs provide hands-on experience in this two-day training and cover the Xilinx Synthesis Technology (XST) tools.
This course requires the Essentials of FPGA Design and Designing for Performance courses as prerequisites. An intermediate knowledge of Verilog or VHDL is strongly recommended as is at least six months of design experience with Xilinx tools and FPGAs. The lecture material in this course covers the ISE 11.3 tools and the Spartan®-6 and
Virtex®-6 FPGAs.
Note: Labs will be based on Xilinx ISE 12.1 software.
Lab 1: Timing Closure Review – Use the Constraints Editor to enter timing constraints.
Lab 2: UCF Editing – Write constraints directly into a UCF file to guide the performance results of implementation.
Lab 3: Advanced I/O Timing–Compose timing constraints for source-synchronous and system-synchronous I/O interfaces. Analyze the timing and determine changes to optimize the interface timing.
Lab 4: Tcl Scripting – Write ISE tool control commands in Tcl script files to create a project and implement the design. Explore how the Tcl interface is integrated with the Project Navigator tool.
Lab 5: SmartGuide Technology – Utilize SmartGuide technology to preserve the timing results from one iteration to the next.
Lab 6: Floorplanning –Implement a design by using floorplanned constraints to improve the timing results over a design without floorplanning.
Lab 7: Advanced FPGA Editor – Use the FPGA Editor to view and edit a design. Rapidly locate and swap signals of interest for ChipScope Pro tool cores.
