Designing with the Spartan-6 and Virtex-6 Families
Are you interested in learning how to effectively utilize Spartan®-6 or Virtex®-6 FPGA architectural resources? This course supports both experienced and less experienced FPGA designers who have already completed the Essentials of FPGA Design course. This course focuses on understanding as well as how to properly design for the primary resources found in these popular device families.
Topics covered include device overviews, CLB construction, DCM and PLL clocking resources, global, regional and I/O clocking techniques, memory, DSP, and source-synchronous resources. Memory controller support and the dedicated hardware resources available in each of the sub-families (EMAC, PCI Express® technology, and GTP transceivers) are also introduced.
This course also includes a detailed discussion about proper HDL coding techniques that enables designers to avoid common mistakes and get the most out of their FPGA.A combination of modules and labs allow for practical hands-on application of the principles taught.
Lab 1: CLB Resources – Gain comprehensive experience with the CLB architecture. Synthesize a 32-bit incrementer with terminal count logic and pipelining registers. Verify that the appropriate resources were used with the RTL and technology viewers included with XST. Use the FPGA Editor to inspect the implemented results.
Lab 2: DSP Resources – Using XST, synthesize and implement a wide MACC. Device usage will be verified via the FPGA Editor. Using the CORE Generator™ tool, construct, instantiate, and
Lab3: I/O Resources – Using the ISE tools, complete the construction of the transmit SERDES datapath. Explore through simulation the behavior of the various blocks. Also use the FPGA Editor to explore the physical resources of the FPGA that are used for construction of a high-speed interface.
Lab 4: Clocking Resources –Using the Clocking Wizard, build and optimize the appropriate PLL, DCM, and clock routing resources. Also instantiate these resources into the design. After the design is implemented, verify hardware usage with the FPGA Editor and explore other aspects of the silicon layout.
Lab 5: HDL Coding Techniques – Using XST, synthesize various components into the design and evaluate the impact that proper HDL coding techniques have on the size and speed of implementation results.
