Xilinx® Authorized Training Provider Courses > FPGA Design/Architecture > Adv. Xilinx Timing Closure w/Synplyfy Pro, XST & PlanAhead
Adv. Xilinx Timing Closure w/Synplyfy Pro, XST & PlanAhead

This custom hybrid course is a fast-paced --lab intensive  curriculum that focuses on Xilinx chip-level optimization when using Synplify Pro® or Xilinx XST® for design entry.  The course covers specific synthesis options that can enhance performance and results. It then covers comprehensive Xilinx timing constraints that are critical to driving the P&R tools.  The course ends with using the PlanAhead®  tool to manage layout, improve timing and enhance repeatability.  This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten development time & lower development costs.

DOWNLOAD FULL COURSE DESCRIPTION



Who Should Attend

 

FPGA designers with intermediate knowledge of HDL and some experience with the Xilinx ISE® software tools

 



At-A-Glance

Schedule
  • Course No:  TSI_19000_COMP
  • Course Duration:  2 Days
  • Price:  USD $1,400
    or 14 Xilinx Training Credits
  • Level: Intermediate
  • Prerequisites

    • Essentials of FPGA Design course or equivalent knowledge of FPGA architecture features; the Xilinx implementation software flow and implementation options; reading timing reports; basic FPGA design techniques; global timing constraints and the Constraints Editor
    • Intermediate HDL knowledge (VHDL or Verilog)
    • Solid digital design background

     

  • Software Tools

            ISE Design Suite: Logic or System Edition 12.1
    PlanAhead 12.1 & Synplify Pro

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COURSE OUTLINE

Day 1

  • Course Introduction
  • Xilinx Timing Closure  Design Overview
  • Synthesis Optimization with Synplify Pro
  • Synthesis Optimization with XST
  • Lab 1: Use Advance Synthesis Options
  • Xilinx FPGA Clocking Resources,  V6, Spartan-6   
  • Lab 2: Create various clocking schemes
  • Comprehensive Timing Constraints
  • Lab 3: Create Detailed Timing Groups

 

Day 2

  • Using Xilinx Timing Analyzer
  • Xilinx PlanAhead ( Part I)
  • Lab 4: Getting started with PlanAhead
  • Xilinx PlanAhead ( Part II)
  • Lab 5: Creating Floorplans, Analyzing Results
  • Xilinx PlanAhead ( Part III)
  • Lab 6: Fine-tuning Floorplans
  • Course Review


LAB DESCRIPTION

Lab 1: Advanced Synthesis Options - For either VHDL or Verilog users, understanding key synthesis options and menu  selections

Lab 2: Create Various Clocking  schemes - Use the Architectural Wizard to create DCM or MMCM components for various clock frequencies and distribution requirements

Lab 3: Create Detailed Timing Groups - Use the Xilinx Constraints Editor to create comprehensive Timing Constraints

Lab 4: Getting Started with PlanAhead - Create projects, perform initial design analysis

Lab 5: Creating Floorplans, Analyzing Results - Create floorplan, implement design, evaluate results

Lab 6: Export IP Module -  Create RPMs for module reuse, portability and deterministic layout

 

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