Attending the Designing for Performance class will help you create more efficient designs. This course can help you fit your design into a smaller FPGA or a lower speed grade for reducing system costs. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.
FPGA designers with intermediate knowledge of HDL and some experience with the Xilinx ISE® software tools.
At-A-Glance
Schedule
Course
No: FPGA23000-ILT
Course Duration: 16:00 HR
Price: USD $1,200
or 12 Xilinx
Training Credits
Level:
Intermediate
Prerequisites
Essentials of FPGA Design course or equivalent knowledge of FPGA architecture features; the Xilinx implementation software flow and implementation options; reading timing reports; basic FPGA design techniques; global timing constraints and the Constraints Editor
Lab 1: Designing with FPGA Resources – Create block RAM and clocking FPGA cores using the CORE Generator™ tool. Instantiate these cores and other clock resources and implement the design.
Lab 2: Synthesis Techniques – Experiment with different synthesis options (including timing constraints, resource sharing, synthesis optimization effort, and register balancing) and view the results.
Lab 3: Review of Global Timing Constraints – Use the Constraints Editor to enter global timing constraints.
Lab 4: Achieving Timing Closure – Review timing reports and enter path-specific timing constraints to fully describe your performance requirements.
Lab 5: Designing for Performance – Improve performance and maximize results solely with implementation options and SmartXplorer.
Lab 6: FPGA Editor Demo (optional) – Use the FPGA Editor to view a design and add a probe to an internal net.
Lab 7: ChipScope Pro Software (optional) – Add an internal logic analyzer to a design to perform real-time debugging.
