Technically Speaking Course Listing | Xilinx® Authorized Training Provider | FPGA Design/Architecture

Essentials of FPGA Design

Use the ISE® software tools to implement a design and gain a firm understanding of the Xilinx FPGA architecture. Learn the best design practices from the pros and understand the subtleties of the Xilinx design flow.

This course covers ISE software 12.1 features, such as the Architecture Wizard, I/O PlannerFCKeditor/userfiles/file/2010CourseDescriptions/Essentials%20of%20FPGA%20Design.pdf, and the Constraints Editor. Other topics include FPGA architecture, good design practices, understanding report contents, and global timing constraints.

For more emphasis on improving the overall design performance, take the follow-up course Designing for Performance, which builds on the basic principles covered in this course.

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Who Should Attend

Digital designers who have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs

At-A-Glance	Schedule
Course No: FPGA13000-ILT Course Duration: 08:00 hr. Price: USD $600 or 6 Xilinx Training Credits Level: Intro / Intermediate Prerequisites Working HDL knowledge (VHDL or Verilog) Digital design experience Software Tools Xilinx ISE Design Suite: Logic or System Edition 12.1	September 20, 2010 San Diego, CA Country Inn & Suites by Carlson 5975 Lusk Blvd. San Diego, CA 92121 tel: 858.200.1955 November 15, 2010 Orange County, CA Doubletree - Orange County Airport 7 Hutton Centre Dr. Santa Ana, California, United States 92707-5794 Tel: 1-714-751-2400 Fax: 1-714-662-7935

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COURSE OUTLINE

Course Agenda
Basic FPGA Architecture
Xilinx Tool Flow
Lab 1: Xilinx Tool Flow
Reading Reports
Lab 2: Clocking Wizard and Pin Assignment
Lab 3: Pre-Assigning I/O Pins Using the PlanAhead Tool
Global Timing Constraints
Lab 4: Global Timing Constraints
Synchronous Design Techniques
Course Summary

LAB DESCRIPTION

Lab 1: Xilinx Tool Flow – Create a new project in the ISE Project Navigator and use the ISE Simulator to perform a behavioral simulation. Implement the design using default software options and download to a Spartan-6 FPGA SP605 evaluation board.

Lab 2: Clocking Wizard and PlanAhead Tool – Use the Clocking Wizard to customize a DCM and incorporate your clocking resources into your design. Use the PlanAhead tool to assign pin locations and implement the design using the Project Navigator in the ISE software.

Lab 3: Pre-Assigning I/O Pins Using the PlanAhead Tool – This lab introduces the basics of making good I/O pin assignments with the PlanAhead software. Perform Weighted Average Simultaneously Switching Output (WASSO) analysis to avoid ground bounce and use the Design Rule Checker to follow the I/O banking rules.

Lab 4: Global Timing Constraints – Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint.