TSI Proprietary Training Courses > Tools > Debugging Techniques Using the ChipScope Pro Tools
Debugging Techniques Using the ChipScope Pro Tools

As FPGA designs become increasingly more complex, designers continue look to reduce design and debug time. The powerful, yet easy-to-use ChipScope™ Pro tool solution helps minimize the amount of time required for verification and debug.

 

This two-day course will not only introduce you to the cores and tools and illustrate how to use the triggers effectively, but also show you effective ways to debug logic and high-speed designs—thereby decreasing your overall design development time. This training will provide hands-on labs that demonstrate how the ChipScope Pro tools can address advanced verification and debugging challenges.

... DOWNLOAD XILINX COURSE DETAIL


 



Who Should Attend

System and logic designers who want to minimize verification and debug time

 

 



At-A-Glance

Schedule
  • Course No:  CSP22000-92
  • Course Duration:  2 Days
  • Price:  USD $1,200
    or 12 Xilinx Training Credits
  • Level: Intro/Intermediate
  • Prerequisites

      Basic language concepts for both days

      o    Designing with VHDL or equivalent knowledge of VHDL

      o    Designing with Verilog or equivalent knowledge of Verilog

      Basic FPGA skills for Day 1

      o    Essentials of FPGA Design

      Intermediate FPGA skills for Day 2

      o    Designing for Performance

      ChipScope Pro Software REL strongly recommended
      (www.xilinx.com/support/training/rel/chipscopepro-rel.htm)

  • Software Tools

     

    Xilinx ISE® Design Suite: Logic or System Edition 12.1

    ChipScope Pro 12.1 software

     
  • October 4-5, 2010
    Orange County, CA
    Doubletree - Orange County Airport

    7 Hutton Centre Dr.

    Santa Ana, California,

    United States 92707-5794


    Tel: 1-714-751-2400   Fax: 1-714-662-7935

     

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COURSE OUTLINE

Day 1

How the ChipScope Pro Tool Works

Inserting the Cores – Inserter Flows: Core Inserter and the PlanAhead Software

Labs 1a and 1b: Using the Inserter Tool from Project Navigator and Using the Inserter Tool from the PlanAhead software

Instantiating the Cores – The CORE Generator Tool Flow

Lab 2: Using the CORE Generator Tool from Project Navigator

Triggering and Storage

Visualizing Data – The ChipScope Pro Analyzer Tool

Lab 3: Triggering and Visualization in the Analyzer Tool

 

Day 2

Tips and Tricks

Lab 4: Tips and Tricks

Time for Timing

Video Demo – Area Groups for Isolation

Case Studies

Lab 5: FPGA Editor Support for the ChipScope Pro Tool

Scripting (Optional)*

Lab 6: VIO Tcl Scripting (Optional)*

Remote Access (Optional)*

Lab 7: Remote Access (Optional)*

 

LAB DESCRIPTION

Labs 1a and 1b: Using the Inserter Tool from Project Navigator (Lab 1a) and Using the Inserter Tool from the PlanAhead Software (Lab 1b) – Insert an ICON and ILA cores into an existing netlist and debug a common problem.

Lab 2: Using the CORE Generator Tool from Project Navigator – Build upon a provided design to create and instantiate a VIO core and observe its behavior using the ChipScope Pro Analyzer tool.

Lab 3: Triggering and Visualization in the Analyzer Tool – Configure triggers and view captured data using the ChipScope Pro Analyzer tool.

Lab 4: Tips and Tricks – Keep time across multiple sample windows; sample across multiple time domains; and implement a complex custom (unconventional) trigger.

Lab 5: FPGA Editor Support for the ChipScope Pro Tool – Change the signals being sampled by an ILA without having to reimplement the design.

Lab 6: VIO Tcl Scripting – Configure automated analysis.

Lab 7: Remote Access – Use the ChipScope Pro Analyzer tool to configure an FPGA, set up triggering, and view the sampled data from a remote location.

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