Learn how to employ RocketIO™ GTP and GTX serial transceivers in your Spartan®-6 LXT or Virtex®-6 FPGA design. Understand and utilize the features of the RocketIO transceiver blocks, such as 8B/10B and 64B/66B encoding, channel bonding, clock correction, and comma detection. Additional topics include use of the Architecture Wizard, synthesis and implementation considerations, board design as it relates to the transceivers, and test and debugging. This course combines lectures with practical hands-on labs.
Lab 1: 8B/10B Disparity and Bypass – Utilize the 8B/10B encoder and decoder and observe running disparity. Learn how to bypass the 8B/10B encoder and decoder.
Lab 2: Commas and Data Alignment – Use programmable comma detection to align a serial data stream.
Lab 3: Clock Correction – Utilize the attributes and ports associated with clock correction to compensate for frequency differences in the TX and RX clocks.
Lab 4: Channel Bonding – Modify a design to use two transceivers bonded together to form one virtual channel.
Lab 5: GTP Wizard – Use the GTP Wizard to create instantiation templates
Lab 6: Implementation and Simulation – Instantiate the transceiver component in a design, synthesize the design, and implement the design.
Lab 7: 64B/66B GTX Transceiver – Generate a 64B/66B GTX core by using the CORE Generator™ tool, simulate the design, and analyze the results.
Lab 8: System – Perform all design steps from planning the design, generation of the core, integration of the core into a design, simulating, implementing and debugging the design, and optimizing the link parameter using an evaluation board.
